<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Systems on Aditya Kurniawan (Akur)</title><link>https://akurniawan.github.io/categories/systems/</link><description>Recent content in Systems on Aditya Kurniawan (Akur)</description><generator>Hugo</generator><language>en-us</language><lastBuildDate>Mon, 14 Sep 2026 00:00:00 +0700</lastBuildDate><atom:link href="https://akurniawan.github.io/categories/systems/index.xml" rel="self" type="application/rss+xml"/><item><title>I Set Out to Learn NRVO and Ended Up Measuring My Command Line</title><link>https://akurniawan.github.io/posts/return-std-move-costs-instructions-not-cycles/</link><pubDate>Mon, 14 Sep 2026 00:00:00 +0700</pubDate><guid>https://akurniawan.github.io/posts/return-std-move-costs-instructions-not-cycles/</guid><description>I wanted to understand named return value optimisation, got curious what the pessimised version costs, and my first numbers were reproducible to 0.01% and wrong. Instructions and cycles instead of wall-clock, and the pointer question turned out to be an allocator question.</description></item><item><title>How I Benchmark on the GB10 CPU</title><link>https://akurniawan.github.io/posts/how-i-benchmark/</link><pubDate>Sun, 13 Sep 2026 00:00:00 +0700</pubDate><guid>https://akurniawan.github.io/posts/how-i-benchmark/</guid><description>The same benchmark landed at 3.47 ms and 7.01 ms on different afternoons while reporting under 0.3% variation both times. These are the habits that survived that.</description></item><item><title>NVLink-C2C Removes the Copy, Not the Synchronization</title><link>https://akurniawan.github.io/posts/nvlink-c2c-what-changes-for-cpp/</link><pubDate>Sun, 06 Sep 2026 00:00:00 +0700</pubDate><guid>https://akurniawan.github.io/posts/nvlink-c2c-what-changes-for-cpp/</guid><description>The CUDA Programming Guide assumes the host and the device keep separate memories with a copy between them. My DGX Spark doesn&amp;rsquo;t. So I went and learned what NVLink-C2C actually is compared to PCIe, how coherence behaves across it, and what that changes for someone writing C++ on this machine.</description></item><item><title>CUDA Performance, Part 1: Device Busy Is Not GPU Busy</title><link>https://akurniawan.github.io/posts/gpu-timeline-gaps/</link><pubDate>Sun, 16 Aug 2026 00:00:00 +0700</pubDate><guid>https://akurniawan.github.io/posts/gpu-timeline-gaps/</guid><description>A program can report 98.8% device utilization while leaving its compute units idle 39% of the time. This is what I learned building a TUI for nsys timelines, and why the second number is the only one that matters.</description></item></channel></rss>